Answer

AES3 connections on the CIAES16 card are balanced for noise immunity, so the RJ45 connector is isolated from chassis ground and its interface uses fully isolated transformers for each wire pair. Most network cable is unshielded and has unshielded connectors but uses twisted wire pairs to help with noise immunity.

Noise and interference problems are therefore exceptionally rare, and the CIAES16's transformers and onboard ESD protection will further suppress spikes that may develop on the network cable.

Nevertheless, a combination of unfavorable conditions—for example, a very long network cable and a noisy lighting controller nearby—could result in  voltage spikes that are too large for the transformers and ESD protection to suppress. If the Q-SYS ecosystem clock is synchronized to the AES3 stream, the spikes could cause processing overruns. That happens when the spikes cause false clock edges lie in between the real clock contained in the bi-phase mark code of the AES3 signal. The false clock edges cause the software-based PLL to lose its lock on the AES3 clock.

To prevent this happening, disable sync to the AES3 signal and enable the CIAES16 sample rate converters. Set this up in the Properties pane in Q-SYS Designer Software as shown below.